1. Field of the Invention
The present invention relates to a digital computer system more particularly to a store buffer device provided between a central processing unit (CPU) and a main storage unit (MSU) for updating memory contents in the MSU to be identical to that in a buffer storage also provided between the CPU and the MSU.
2. Description of the Related Art
In a digital computer system for high speed data processing, it is possible to improve the substantive access time from a CPU to an MSU having a large memory capacity by providing a buffer storage (cache memory) between the CPU and the MSU.
Data required for processing the in CPU is transferred in advance from a corresponding memory area in the MSU to a predetermined memory area in the buffer storage. Thus, the CPU can store data in or read data from the buffer storage, instead of the MSU, at a higher access speed.
The buffer storage, however, generally has a smaller memory capacity than the MSU. When the buffer storage is full and new data must be placed in the buffer storage, the memory contents in a certain region of the buffer storage, having a size greater than the memory capacity required for the new data, must be replaced with the new data. The memory content replaced is that for which access is requested least frequently or that whose access was requested the longest time ago. As a consequence, the data to be replaced must be restored to the corresponding area in the MSU before the new data is transferred to the buffer storage.
To update stored data in a buffer storage, two approaches are known: a swapping method and a store-through method. The present invention pertains to the store-through method.
To clarify the difference between the two approaches, however, the swapping method will be explained in brief. In the swapping method, the CPU performs both read and store operations with the buffer storage when the required data exists in the buffer storage. If the CPU requires new data to be placed in the buffer storage, the CPU first seeks a suitable vacant area in the buffer storage which can accommodate the new data and transfers the data in the MSU to the vacant area. When there is no suitable vacant area in the buffer storage, it performs a swapping operation. Specifically, the CPU seeks a suitable erasable area in the buffer storage, moves current data stored in the erasable area to the corresponding area in the MSU, and transfer the required data in the MSU to the erasable area in the buffer storage. In comparison with the store-through method, keeping data in the MSU identical to that in the buffer storage is somewhat more complex. On the other hand, it is not necessary to provide any additional store buffer devices.
In the store-through method, the CPU stores data in the MSU simultaneously with storing data in the buffer storage, the data stored in the MSU being identical to that stored in the buffer storage. As a result, the memory content in the MSU is kept identical to the current memory content in the buffer storage. When new data is to be placed in the buffer storage, the required new data can therefore be transferred from the MSU to a suitable area in the buffer storage without a swapping operation by just writing over the contents of the buffer area.
The primitive store-through method mentioned above, however, obviously reduces the CPU performance, cancelling out the merits of provision of a buffer storage, since a direct store operation from a CPU to an MSU requires a longer time than that of a buffer storage and the CPU must await completion of the store operation in the MSU. In order to overcome this problem, a store buffer device is normally provided between the CPU and the MSU, separate from the buffer storage and independently operable from the buffer storage.
The store buffer device mainly consists of a plurality of registers, each having a higher operation time than the buffer storage. With a store buffer device, the CPU can transmit data identical to that to be stored in the buffer storage and a control signal therefor to the store buffer device at the same time as storing data in the buffer storage. When an acknowledge signal is received from the store buffer device, which means the store buffer device has received the data and the control signals, the CPU proceeds with the next step after completion of the store operation in the buffer storage without waiting for completion of the store operation in the MSU. The store buffer device can transmit the data and the control signals temporarily held therein to the MSU at any time, independent of the operation of the CPU and the buffer storage. The received data is actually stored in the corresponding memory area in the MSU in accordance with the received control signals. As can be clearly understood, due to the provision of the store buffer device the CPU is free from the reduced performance incumbent with direct storage of data in the MSU.
Prior art computer systems based on the store-through method, however, still suffer from some disadvantages. The prior store buffer device consists of a plurality of buffer sets, for example, five sets, a control circuit cooperating therewith, and buffer registers provided between the CPU and the buffer sets and commonly used for receiving data and control signals thereof. Each buffer set includes a data register for temporarily storing data received from the CPU through the buffer register, a byte mark register for holding flags indicating storable data bytes in the data registers, and an address register for holding a starting storage address in the MSU for the data bytes in the data register. Each data register has a predetermined bit length, defined by, for example, a plurality of bytes to receive a plurality of data bytes to be stored in the MSU from the CPU upon a store request from the CPU.
Data of a plurality of bytes to be transmitted to the store buffer device at a single store request is defined by the transmission capacity between the CPU and the store buffer device during a machine cycle of the CPU. The plurality of data bytes to be transferred to the MSU from the store buffer device at a transfer command is defined by the transfer capacity between the store buffer device during a machine cycle of the CPU. This is because all devices in the computer system should be synchronized with the machine cycle.
The desired byte number of each data register is set, for example, to eight (8) bytes considering the above.
Obviously, requests are not always for all the data bytes in the data register, thus the data byte mark register must indicate those data bytes to be stored. The data byte mark register is composed of a plurality of bits corresponding to the plurality of bytes of the data register and indicated the data bytes to be stored.
A plurality of store buffer sets is provided to avoid a reduction in the performance of the CPU when many store requests consecutively arise during a short period or when a store request is made for a plurality of data bytes exceeding the capacity of one data register. If there were only one store buffer set, in the first case, the register in the store buffer set might not be empty when the next store request arose and, thus, the CPU would have to wait until the registers became free after reception of an acknowledge signal from the MSU. In the second case, the CPU would have to divide and transmit a plurality of store requests each with a plurality of data bytes equal to or less than the length of one data register with, accordingly, the same adverse situation as mentioned above.
Even when the prior art store buffer device includes a plurality of store buffer sets, the prior art digital computer system is adversely affected in its access of storage data by the inherent delay between the store buffer device and the MSU. Normally, a circuit for a store buffer device is installed on the same printed circuit (PC) board as the circuit of the CPU or on another PC board adjacent to the PC board for the circuit of the CPU, so that each store request to the store buffer device can be accepted during a single machine cycle. On the other hand, the store buffer device is located a relatively great distance from the MSU. The considerable distance between the store buffer device and the MSU requires a longer signal propagation time, for example, two machine cycles: one for data transmission to the MSU and one for reception of an acknowledge (ACK) signal from the MSU, as shown in FIG. 1.
Note that, even in the prior art system, upon receipt of store request(s) from the CPU, the store buffer device first transmits to the MSU data bytes kept in the data register and control signals thereof kept in the byte mark register and the address register at a machine cycle 1 in FIG. 1. After receipt of the acknowledge signal from the MSU at a machine cycle 2 in FIG. 1, the store buffer device can transmit to the MSU the next data bytes and control signals, if any exist, at a machine cycle 3 in FIG. 1 without waiting until completion of the storage of the first data bytes in the MSU. This helps eliminate the delay in the store buffer device, thus increasing the availability of the store buffer device for acceptance of new store requests from the CPU and, thus, reducing the probability of waiting for queuing to the store buffer device in the CPU.
On the other hand, it is clear that two machine cycles are required for transferring data bytes in one data register to the MSU. The number of machine cycles increases along with the distance between the store buffer device and the MSU.
With a store buffer device consisting of five store buffer sets and data byte registers of eight bytes each and, for example, a data series consisting of a first data set of six data bytes, a second data set of 16 data bytes, a third data set of 16 data bytes a fourth data set of eight data bytes, and a fifth data set of five data bytes, 14 machine cycles are required for storing the series, even in an ideal condition under which no waiting time occurs in the store buffer device. The 14 machine cycles consist of two machine cycles each for the first, fourth, and fifth data sets and four machine cycles each for the second and third data sets. In the case of a consecutive store request in a short period, the number of machine cycles would further increase due to the waiting time in the CPU and in the store buffer device.
The longer access tiime between the store buffer device and the MSU is a first disadvantage in the prior art.
Another disadvantage in the prior art computer system is a lack of flexibility of formation of data, due to the need to set data into the data register with reference to a starting store address in the address register. This will be described later with reference to embodiments of the present invention. This disadvantage may finally lead to a reduction in the performance of the CPU.
The above disadvantages may be particularly serious in an ultra-high speed digital computer system, for example, a computer system having a plurality of arithmetic units for forming a pipline processing machine. This disadvantages may also be increased when a great deal of data is to be stored at one store request or in a short period.